Researchers at IIT Guwahati have achieved new advances in memory architectures in order to solve computer system domain difficulties.
NEW DELHI: Researchers from the Indian Institute of Technology, Guwahati, have contributed to memory designs by reducing data redundancy and enhancing sluggish and frequent writes in multi-core processing systems. According to a release from IIT Guwahati, researchers have devised techniques to handle challenges in the computer systems domain at a time when the globe is quickly shifting toward research in applied fields.
“The application data access patterns are not evenly distributed and so results to multiple orders of writes to particular memory regions compared to others,” said Hemangee K Kapoor, department of CSE, IIT Guwahati, when discussing the problems. Such heavily written regions are susceptible to wear, preventing the usage of complete memory devices without error corrections.” They’re also being extended to off-chip main memory, according to the team.
The future problems will be to deal with lifetime enhancement in the presence of encryption technologies used to safeguard non-volatile memory, as well as to deal with temperature and process technology-driven disturbance faults generated when cells are read or written,” she noted.
IIT Guwahati researchers developed ways to equally disperse accesses over the whole memory capacity to lessen wear-out pressure on heavily written areas to deal with this non-uniformity, according to the IIT Guwahati statement.
The current and future contributions of the researcher will aid in overcoming the disadvantages of potential new memories and facilitating their adaptability. Scientists can identify novel ways for exploiting such technologies without worrying about their restrictions once some negatives are simply eradicated, according to the statement.
